Bench Press

You better believe it. In an effort to push computing power forward and circumvent the traditional problems that go along with a two dimensional chip structure, Eby Friedman and other researchers at the University of Rochester have developed  three dimensional processor capable of running up to 1.4 GHz. This design is supposedly the first of its kind and may be the prototype of the next generation processor and, possibly, a means to rolling out the extra computational power needed for next-generation supercomputers for scientific computing.

Nowadays, the problem with building super-fast processors using a traditional two dimensional structure is that we are reaching the limit on how many transistors we can cram in a given space. This inherently limits the capabilities of a processor and will provide an upper bound on how effective future processors can be. However, by adding one more dimension, processor designers can bypass the usual restrictions and allow for continuing growth in this industry. Additionally, because of the three dimensional structure, new chips can be folded into a tenth the size of their flatter counterparts, yet run at ten times the speed. Such changes could deliver new types of processing capabilities by implementing more complex circuitry than what is allowed in a 2D chip layout:

• Parallel computing: 3D chips will be better able to run computations in parallel by literally stacking individual processes next to and on top of one other
• Memory bandwidth: One of the most important considerations in chip design today is giving processing cores sufficient access to memory such that the cores aren’t left idle during peak computing cycles. 3D chips enable new paths and architectures for memory access which “flat” chip design do not, making systems much faster.
• Reduced energy consumption: Smaller package size and enhanced parallelism will reduce power consumption, making supercomputers/servers consume less power.

However, like all new technologies in their development stage, increasing the complexity of processors introduces several new problems. Synchronizing operating speeds, power requirements, and signal processing are just some of the new concerns chip designers need to deal with.

Friedman says getting all three levels of the 3-D chip to act in harmony is like trying to devise a traffic control system for the entire United States—and then layering two more United States above the first and somehow getting every bit of traffic from any point on any level to its destination on any other level—while simultaneously coordinating the traffic of millions of other drivers.

While 3D chip design is still in its infancy, Professor Friedman’s research group has demonstrated what may one day be the driver for a whole lot of computing power.